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31 mhz , dual programmable filters and variable gain amplifiers data sheet ADRF6516 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no re sponsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise un der any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 C 2012 analog devices, inc. all rights reserved. features matched p air of p rogrammable f ilters and vgas continuous gain control range: 50 db digital gain c ontrol: 15 db 6 - pole butterworth filter : 1 mhz to 31 mhz in 1 mhz step s , 1 db corner f requency preamplifi er and postamplifier gain steps imd3 : >6 5 db c for 1 . 5 v p - p composite output hd2, hd3 : > 6 5 dbc for 1.5 v p - p output differential i nput and o utput flexible output and input common - mode ranges optional dc offset co mpensa tion loop spi programmable filter corners and gain steps power - down f eature single 3.3 v s upply o peration applications baseband i q receivers diversity receivers adc drivers point - to - point and point - to - multipoint radio instrumentation medical functional block dia gram enb l vpsd comd le clk dat a sdo com vps opp1 opm1 com gain vocm com opm2 opp2 inp1 inm1 vps ADRF6516 com vicm ofs1 vps com inp2 inm2 vps com ofds ofs2 vps spi 09422-001 figure 1. general description the ADRF6516 is a matched pair of fully differential , low noise and low distortion programmable filters and variable gain ampl i fiers (vgas) . each channel is capable of rejecting large out - of - band interferers while rel iably boosting the desired signal, thus reducing the bandwidth and resolution requirements on the analog - to - digital converters (adcs). the excellent matching between channels and their high spurious - free dynamic range over all gain and bandwidth settings m ake the ADRF6516 ideal for quadrature - based (iq) communication systems with dense constellations, multiple carriers, and nearby interferers. the filters provide a six - pole butterworth response with 1 db corne r frequencies programma ble through the spi port from 1 mhz to 31 mhz in 1 mhz step s . the pre amplifier that precedes the filters offers a spi - programmable option of either 3 db or 6 db of gain. the preamplifier sets a differential input impedance of 1600 and has a common - mode voltage that defaults to vps/2 but can be driven from 1. 1 v to 1 .8 v. the variable gain amplifiers tha t follow the filters provide 5 0 db of continuous gain control with a slope of 15.5 mv/db. their maximum gains can be programmed to v arious values through the spi. the output buffers provide a differential output impedance of 3 0 ? and are capable of driving 2 v p - p into 1 k ? loads. the output common - mode voltage defaults to v ps /2 , but it can be adjusted down to 7 00 mv by driving the high impedance vocm pin. independent, built - in dc offset co mpensa tion loop s can be disabled if ful ly dc - coupled operation is desired. the high - pass corner frequency is defined by external capacitors on the ofs1 and ofs2 pin s and the vga gain . the ADRF6516 operates from a 3 .1 5 v to 3 .4 5 v supply and consu mes a maximum su p ply current of 36 0 ma when programmed to the highest bandwidth setting. when disabled, it consume s < 9 ma. the ADRF6516 is fabricated in an advanced silicon - germanium bicmos process and is ava ilable in a 32 - lead , exposed paddle lfcsp. performance is specified over the ?4 0 c to +85 c temperature range.
ADRF6516 data sheet rev. b | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing diagrams .......................................................................... 5 a bsolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 register map and codes ................................................................ 15 theory of operation ...................................................................... 16 input buffers ............................................................................... 16 programmable filters ................................................................. 16 variable gain amplifiers (vgas) ............................................ 17 output buffers/adc drivers ................................................... 17 dc offset compensation loop ................................................ 17 programmin g the filters and gains ......................................... 18 noise characteristics ................................................................. 18 distortion characteristics ......................................................... 19 maximizing the dynamic range .............................................. 19 key parameters for quadrature - based receivers .................. 20 applications information .............................................................. 21 basic connections ...................................................................... 21 supply decoupling ..................................................................... 21 input signal path ........................................................................ 21 output signal path ..................................................................... 21 dc offset compensation loop enabled ................................ 21 commo n - mode bypassing ....................................................... 21 serial port connections ............................................................. 22 enable/disable function ........................................................... 22 error vector magnitude (evm) performance ........................... 22 evm test setup .......................................................................... 22 effect of filter bandwidth on evm ......................................... 22 effect of output voltage levels on evm ................................ 23 effect of c ofs value on ev m ..................................................... 23 evaluation board ............................................................................ 24 evaluation board control software ......................................... 24 schematics and artwork ........................................................... 25 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 29 revision history 2/12 rev. a to rev. b changes to figure 57 ...................................................................... 24 changes to figure 58 ...................................................................... 25 added figure 59 .............................................................................. 2 6 ch anges to figure 60 and figure 61 ............................................. 27 changes to table 6 .......................................................................... 27 9 /1 1 revision a : initial version
data sheet ADRF6516 rev. b | page 3 of 32 specifications v p s = 3.3 v, t a = 25c, z l o ad = 1 k ?, digital gain code = 111, unless otherwise noted. table 1 . parameter test conditions/comments min typ max unit frequency response low -p ass corner frequency, f c 6 - pole butterworth filter , 0. 5 db bandwidth 1 31 mhz step siz e 1 mhz corner frequency absolute accuracy over operating temperature range 15 % f c corner frequency matching channel a and channel b at same gain and bandwidth setting s 0.5 % f c pass -b and r ipple 0.5 db p -p gain matching channel a and chann el b at same gain and bandwidth setting s 0.1 db group delay variation from mid band to peak corner frequency = 1 mhz 135 ns corner frequency = 3 1 mhz 11 ns group delay matching channel a and channel b at same gain corner frequency = 1 mhz 5 ns corner frequency = 31 mhz 0.2 ns stop - band rejection relative to pass band 2 f c 30 db 5 f c 75 db input stage inp1, inm1, inp2, inm2 , vicm pins maximum input swing at minimum gain, v gain = 0 v 1 v p - p differential i nput impedance 1600 ? input c ommon - mode range 0.4 v p -p i nput voltage , hd3 > 65 dbc 1.1 1.65 1.8 v input pins left floating vps/2 v vicm output impedance 7 k? gain control gain pin voltage gain range v gain from 0 v to 1 v ?5 + 45 db gain slope 15.5 mv/db g ain error v gain from 3 00 mv to 800 mv 0.2 db output stage opp1, opm1, opp2, opm2, vocm pins maximum output swing at maximum gain, r load = 1 k? 2 v p -p hd2 > 6 5 db c, hd3 > 6 5 db c 1.5 v p - p differential output impedance 3 0 ? output dc o ffs et inputs s horted, offset loop disabled 35 mv output common - mode range 0.7 1.65 2.8 v vocm pin left floating vps /2 v vo cm in put impedance 23 k? noise/distortion corner frequency = 1 mhz output noise density gain = 0 db at f c /2 ? 1 4 1 dbv/hz gain = 2 0 db at f c /2 ?1 31 dbv/hz gain = 4 0 db at f c /2 ?1 1 2 dbv/hz second harmonic , hd2 250 khz fundamental, 1.5 v p -p output voltage gain = 5 db 8 2 dbc gain = 40 db 68 dbc third harmonic , hd3 250 khz fundamental, 1.5 v p - p output voltage gain = 5 db 7 1 dbc gain = 40 db 56 dbc
ADRF6516 data sheet rev. b | page 4 of 32 parameter test conditions/comments min typ max unit imd3 f1 = 500 khz , f2 = 550 khz , 1.5 v p -p composite output voltage gain = 5 db 61 dbc gain = 35 db 42.5 dbc imd3 w ith input cw blocker f1 = 500 khz, f2 = 550 khz, 1.5 v p -p composite outpu t , g ain = 5 db ; blocker at 5 mhz, 10 dbc relative to two - tone composite output voltage 40 dbc corner frequency = 3 1 mhz output noise density mid band, gain = 0 db ?1 43.5 dbv/hz mid band, gain = 2 0 db ?1 3 9 dbv/hz mid band, gain = 4 0 db ?1 2 5 dbv/hz second harmonic , hd2 8 mhz fundamental, 1.5 v p - p output voltage g ain = 5 db 68 dbc gain = 4 0 db 70 dbc third harmonic , hd3 8 mhz fundamental, 1.5 v p - p output voltage g ain = 5 db 5 5 dbc gain = 4 0 db 75 dbc imd3 f1 = 1 4 mhz, f2 = 1 5 mhz, 1.5 v p - p composite output voltage g ain = 5 db 5 5 dbc gain = 3 5 db 77.5 dbc imd3 with input cw blocker f1 = 1 4 mhz , f2 = 1 5 mhz , 1.5 v p -p c omposite output, gain = 5 db ; blocker at 150 mhz, 10 dbc relative to two - tone composite output voltage 55 dbc digital logic le, clk, data, sdo, ofds pins input high voltage , v inh >2 v input low voltage , v inl < 0.8 v input current , i inh /i inl < 1 a input capacitance , c in 2 pf spi timing le, clk, data, sdo pins (see figure 2 and figure 3 ) f sclk 1/t sclk 20 mhz t dh data hold time 5 ns t ds data se tup time 5 ns t lh le hold time 5 ns t ls le setup time 5 ns t pw clk high pulse width 5 ns t d clk to sdo delay 5 ns power and enable vps, vpsd, com, comd, enbl pins supply voltage range 3.1 5 3.3 3.45 v total supply current enbl = 3.3 v corner frequency = 31 mhz 360 ma corner frequency = 1 mhz 330 ma disable current enbl = 0 v 9 ma disable threshold 1.6 v enable response time delay following enbl low -to - high transition 20 s disable response time delay following enb l high - to - low transition 300 ns
data sheet ADRF6516 rev. b | page 5 of 32 timing diagrams write bit msb - 2 b2 lsb t ds t dh t lh t ls t pw t clk notes 1. the first data bit determines whether the part is writing to or reading from the internal 8-bit register. for a write operation, the first bit should be a logic 1. the 8-bit word is then written to the data pin on consecutive rising edges of the clock. clk le data b3 b7 msb b4 b5 b6 09422-003 figure 2 . write mode timing diagram don?t care don?t care read bit don?t care don?t care don?t care don?t care don't care b2 lsb clk le dat a sdo notes 1. the first data bit determines whether the part is writing to or reading from the internal 8-bit register. for a read operation, the first bit should be a logic 0. the 8-bit word is then registered at the sdo pin on consecutive falling edges of the clock. b3 b4 b5 b6 b7 msb don?t care don?t care t ds t dh t lh t ls t pw t clk t d 09422-004 figure 3 . read mode timing diagram
ADRF6516 data sheet rev. b | page 6 of 32 absolute maximum rat ings table 2 . parameter ra ting supply voltages , vps, vpsd 3.4 5 v enbl, ofds, le, clk, data, sdo vps d + 0.5 v inp1, inm1, inp2, inm2 vps + 0.5 v opp1, opm1, opp2, opm2 vps + 0.5 v ofs1, ofs2 vps + 0.5 v gain vps + 0.5 v internal power dissipation 1.25 w ja ( exposed pad sold ered to board) 37.4 c/w maximum junction temperature 1 50 c operating temperature range ?40 c to +85 c storage temperature range ?65 c to +150 c lead temperature (soldering 60 sec) 300 c stresses above those listed under absolute maximum ratings may c ause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum ratin g conditions for extended periods may affect device reliability. esd caution
data sheet ADRF6516 rev. b | page 7 of 32 pin configuration an d function descripti ons pin 1 indic a t or 1 vpsd 2 comd 3 le 4 clk 5 dat a 6 sdo 7 com 8 vps 24 opp1 23 opm1 22 com 21 gain 20 vocm 19 com 18 opm2 17 opp2 9 com 10 inp2 1 1 inm2 12 vps 13 com 14 ofds 15 ofs2 16 vps 32 enb l 31 inp1 30 inm1 29 vps 28 com 27 vicm 26 ofs1 25 vps t op view (not to scale) ADRF6516 09422-002 notes 1. connect the exposed p addle t o a low impedance ground p ad. figure 4 . pin configuration table 3 . pin function descriptions pin o. mn emonic description 1 vpsd digital positive supply voltage: 3 . 1 5 v to 3. 4 5 v. 2 comd digital common. c onnect to external circuit common using the lowest possible impedance. 3 le latch enable. spi p rogramming p in . ttl levels : v low < 0.8 v, v high > 2 v . 4 clk spi port clock. ttl levels : v low < 0.8 v, v high > 2 v . 5 data spi data input. ttl levels : v low < 0.8 v, v high > 2 v . 6 sdo spi data output. ttl levels : v low < 0.8 v, v high > 2 v . 7, 9, 13, 19, 22, 28 com analog common. connect to external circuit c ommon using the lowest possible impedance. 8, 12, 16, 25, 29 vps analog positive supply voltage: 3.1 5 v to 3. 4 5 v. 10, 11, 30, 31 inp 2 , in m 2 , in m1 , i np1 differential inputs . 16 00 ? input impedance. 14 ofds offset co mpensa tion loop disable . pull high to disable the offset compensation loop . 15, 26 ofs 2 , ofs 1 offset compensation loop capacitors . connect capacitors to circuit common. 17, 18, 23, 24 opp 2, opm2 , opm1, opp 1 differential outputs . 3 0 ? out put impedance. common - mode range is 0. 7 v to 2 .8 v; de fault i s vps/2. 20 vocm output common -m ode setp oin t. defaults to vps /2 if left floating . 21 gain analog gain control . 0 v to 1 v, 15.5 mv/db gain scaling. 27 vicm input common - mode voltage. vps/2 v reference. use to reference the optimal common - mode dr ive to the differential inputs. 32 enbl chip enable . pull high to enable. ep exposed paddle . connect the exposed paddle to a low impedance ground pad.
ADRF6516 data sheet rev. b | page 8 of 32 typical performance characteristics vps = 3.3 v, t a = 25c, z load = 1 k?, digital gain code = 111, unless otherwise noted. ?10 ?5 0 5 10 15 20 25 30 35 40 45 50 0 100 200 300 400 500 600 700 800 900 1000 gain (db) v gain (mv) bandwidth = 31mhz ?40c vps = 3.15 v , 3.3 v , 3.45v +85c vps = 3.15 v , 3.3 v , 3.45v +25c vps = 3.15 v , 3.3 v , 3.45v 09422-005 figure 5 . in - band gain vs. v gain over supply and temperature ( bandwidth setting = 31 mhz ) ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 45 50 1 10 100 gain (db) frequenc y (mhz) bandwidth = 31mhz 09422-006 figure 6. gain vs. frequency over v gain ( bandwidt h setting = 31 mhz ) ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 0 100 200 300 400 500 600 700 800 900 1000 gain mism a tch (db) v gain (mv) bandwidth = 31mhz 09422-007 figure 7. gain matching vs. v g ain ( bandwidth setting = 31 mhz ) ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 100 200 300 400 500 600 700 800 900 1000 gain error (db) v gain (mv) ?40c vps = 3.15 v , 3.3 v , 3.45v +25c vps = 3.15 v , 3.3 v , 3.45v +85c vps = 3.15 v , 3.3 v , 3.45v 09422-008 bandwidth = 31mhz figure 8. gain conformance vs. v gain over supply and temperature ( bandwidth setting = 31 mhz ) ?2 ?1 0 1 2 3 4 5 6 7 8 ?15 ?14 ?13 ?12 ?1 1 ?10 ?9 ?8 ?7 ?6 ?5 0 5 10 15 20 25 30 35 amplitude (db) gain ste p (db) frequenc y (mhz) bandwidth = 31mhz digi t al gain = 11 1 digi t al gain = 0 1 1 09422-009 figure 9. gain step and gain error vs. frequency ( bandwidth setting = 31 mhz , v gain = 0 v) 8 9 10 1 1 12 13 14 ?30 ?25 ?20 ?15 ?10 ?5 0 0 5 10 15 20 25 30 35 gain ste p (db) amplitude (db) frequenc y (mhz) digi t al gain = 0 1 1 digi t al gain = 000 bandwidth = 31mhz 09422-010 figure 10 . gain step and gain error vs. frequency (bandwidth setting = 31 mhz, v gain = 0 v )
data sheet ADRF6516 rev. b | page 9 of 32 ?20 ?15 ?10 ?5 0 5 10 15 20 0 5 10 15 20 25 30 35 40 op1db (dbv) gain (db) digi t al gain = 11 1 bandwidth = 31mhz digi t al gain = 000 09422-0 1 1 figure 11 . output p1db vs. gain at 15 mh z ( bandwidth setting = 31 mhz ) ?10 ?5 0 5 10 15 20 25 30 35 40 1 10 100 gain (db) frequenc y (mhz) 09422-012 figure 12 . frequency response vs. bandwidth setting (gain = 30 db ), log scale ?10 ?5 0 5 10 15 20 25 30 35 40 0 10 20 30 40 50 60 70 80 90 100 gain (db) frequenc y (mhz) 09422-013 figure 13 . frequency response vs. bandwidth setting ( gain = 30 db ), linear scale 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 ?40c, vps = 3.15 v , 3.3 v , 3.45v +25c, vps = 3.15 v , 3.3 v , 3.45v +85c, vps = 3.15 v , 3.3 v , 3.45v gain (db) v gain (mv) bandwidth = 31mhz 09422-014 figure 14 . frequency respo nse over supply and temperature ( bandwidth setting = 31 mhz , gain = 30 db ) 0 100 200 300 400 500 600 700 800 900 1000 0.3 3 30 grou p del a y (ns) frequenc y (mhz) bw = 1mhz bw = 5mhz bw = 10mhz bw = 20mhz bw = 31mhz 50 gain = 20db 09422-015 figure 15 . group delay vs. frequency (gain = 2 0 db ) ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0.3 3 30 grou p del a y mism a tch (ns) frequenc y (mhz) bandwidth = 31mhz gain = 40db gain = 20db 09422-016 figure 16 . group delay matching vs. frequency (bandwidth setting = 31 mhz )
ADRF6516 data sheet rev. b | page 10 of 32 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 0.2 0.4 0.6 0.8 1.0 1.2 1.4 grou p del a y mism a tch (ns) frequenc y (mhz) bandwidth = 1mhz gain = 20db gain = 0db 09422-017 figure 17 . iq group delay matching vs. frequency (bandwidth setting = 1 mhz ) ?0.50 ?0.25 0 0.25 0.50 0 5 10 15 frequenc y (mhz) frequenc y (mhz) 20 25 30 0 0.5 1.0 1.5 2.0 2.5 3.0 amplitude mism a tch (db) bandwidth = 30mhz bandwidth = 1mhz 09422-018 figure 18 . iq amplitude match i ng vs. frequency 0 10 20 30 40 50 60 70 80 90 0 5 10 15 20 25 30 35 40 45 hd2 a t 16mhz (dbc) gain (db) +2 5 c, vps = 3.3v +2 5 c, vps = 3.15v +2 5 c, vps = 3.45v +8 5 c, vps = 3.3v +8 5 c, vps = 3.15v +8 5 c, vps = 3.45v ?4 0 c, vps = 3.3v ?4 0 c, vps = 3.15v ?4 0 c, vps = 3.45v 09422-019 figure 19 . hd2 vs. gain over supply and temperature (bandwidth setting = 31 mhz , 1.5 v p - p, 8 mhz cw fundamental output ) 30 40 50 60 70 80 90 0 5 10 15 20 25 30 35 40 45 hd2 a t 16mhz (dbc) gain (db) vocm = 0.9v vocm = 1.2v vocm = 1.4v vocm = 1.65v 09422-020 figure 20 . hd2 vs. gain over output common - mode voltage (ba ndwidth setting = 31 mhz , 1.5 v p - p, 8 mhz cw fundamental output) 0 10 20 30 40 50 60 70 80 90 0 5 10 15 20 25 30 35 40 45 hd3 a t 24mhz (dbc) gain (db) +25c, vps = 3.3v +25c, vps = 3.15v +25c, vps = 3.45v +85c, vps = 3.3v +85c, vps = 3.15v +85c, vps = 3.45v ?40c, vps = 3.3v ?40c, vps = 3.15v ?40c, vps = 3.45v 09422-022 figure 21 . hd3 vs. gain over supply and temperature (bandwidth setting = 31 mhz , 1.5 v p - p, 8 mhz cw fundamental output) 30 40 50 60 70 80 90 0 5 10 15 20 25 30 35 40 45 hd3 a t 24mhz (dbc) gain (db) vocm = 0.9v vocm = 1.2v vocm = 1.4v vocm = 1.65v 09422-023 figure 22 . hd3 vs. gain over output common - mode voltage (bandwidth setting = 31 mhz, 1.5 v p - p, 8 mhz cw fundamental output)
data sheet ADRF6516 rev. b | page 11 of 32 50 55 60 65 70 75 80 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 harmonic distortion (dbc) vicm (v) gain = 0db, hd2 gain = 0db, hd3 gain = 10db, hd2 gain = 10db, hd3 09422-024 figure 23. hd2 and hd3 vs. input common-mode voltage (bandwidth setting = 31 mhz, 0.4 v p-p input level) 0 5 10 15 20 25 30 35 40 45 50 oip3 (dbv) gain (db) digital gain = 000 digital gain = 111 bandwidth = 31mhz f1 = 14mhz, f2 = 15mhz 09422-025 0 5 10 15 20 25 30 35 40 45 figure 24. in-band oip3 vs. gain (bandwidth setting = 31 mhz) 0 5 10 15 20 25 30 35 40 45 50 oip3 (dbv) gain (db) bandwidth = 31mhz f1 = 14mhz, f2 = 15mhz digital gain = 111 ?40c +85c 09422-026 0 5 10 15 20 25 30 35 40 45 +25c figure 25. in-band oip3 vs. gain over temperature (bandwidth setting = 31 mhz) 10 20 30 40 50 60 70 80 90 100 110 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 imd3 (dbc) composite output voltage (v p-p) gain = 30db gain = 20db gain = 10db gain = 0db 09422-027 figure 26. in-band third-order intermodulation distortion (bandwidth setting = 31 mhz, digital gain = 000) 0 10 20 30 40 50 60 70 80 90 100 imd3 (dbc) gain = 40db gain = 30db gain = 20db gain = 10db gain = 0db 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 composite output voltage (v p-p) 09422-028 figure 27. in-band third-order intermodulation distortion (bandwidth setting = 31 mhz, digital gain = 111) ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 ?55 ?45 ?35 ?25 ?15 ?5 5 15 25 35 45 55 65 imd2 a t 15mhz (dbv) input level at 115mhz and 130mhz (dbv/tone) out-of-band iip2 preamp gain = 3db preamp gain = 6db 2:1 slope bandwidth = 31mhz 09422-029 figure 28. out-of-band iip2, imd2 tone at midband (bandwidth setting = 31 mhz)
ADRF6516 data sheet rev. b | page 12 of 32 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 imd3 a t 15mhz (dbv) input level at 115mhz and 215mhz (dbv/tone) 3:1 slope bandwidth = 31mhz out-of-band iip3 preamp gain = 3db preamp gain = 6db 09422-030 figure 29. out-of-band iip3, imd3 tone at midband (bandwidth setting = 31 mhz) 10 15 20 25 30 35 40 45 50 55 60 ?20?10 0 1020304050 nf (db) gain (db) digital gain = 000 digital gain = 100 digital gain = 110 digital gain = 111 09422-031 figure 30. noise figure vs. analog gain over digital gain (bandwidth setting = 31 mhz, noise figure at 1/2 bandwidth) 20 25 30 35 40 45 50 ?5 5 15253545 nf (db) gain (db) 09422-032 1mhz 2mhz 4mhz 8mhz 16mhz 31mhz figure 31. noise figure vs. ga in over bandwidth setting (digital gain = 111, noise figure at 1/2 bandwidth) ?150 ?155 ?160 ?130 ?135 ?140 ?145 ? 110 ?115 ?120 ?125 ?20?10 0 1020304050 output noise density (dbv/ hz) gain (db) 09422-033 digital gain = 000 digital gain = 100 digital gain = 110 digital gain = 111 figure 32. output noise density vs. analog gain over digital gain (bandwidth setting = 31 mhz, measured at 1/2 bandwidth) ?150 ?140 ?145 ?120 ?125 ?130 ?135 ? 100 ?105 ?110 ?115 ?5 51525354550 010203040 output noise density (dbv/ hz) gain (db) 09422-034 1mhz 2mhz 4mhz 8mhz 16mhz 31mhz figure 33. output noise density vs . gain over bandwidth setting (digital gain = 111, measured at 1/2 bandwidth) ?150 ?145 ?140 ?135 ?130 ?125 ?120 ?115 ?110 ?105 ? 100 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 output noise density (dbv/ hz) frequency (mhz) gain = 20db gain = 0db gain = 40db bandwidth = 1mhz digital gain = 111 09422-052 figure 34. output noise density vs. frequency (bandwidth setting = 1 mhz, digital gain = 111)
data sheet ADRF6516 rev. b | page 13 of 32 ?150 ?145 ?140 ?135 ?130 ?125 ?120 ?1 15 ?1 10 5 15 25 35 45 55 65 75 85 95 output noise density (dbv/hz) frequency (mhz) bandwidth = 31mhz digi t al gain = 11 1 gain = 20db gain = 0db gain = 40db 09422-051 figure 35 . output noise density vs. frequency (bandwidth setting = 31 mhz , digital gain = 111 ) ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 output noise densit y a t 15mhz (dbv/hz) blocker leve l a t 150mhz (dbv rms) 09422-037 ?145 ?140 ?135 ?130 ?125 ?120 ?1 15 ?1 10 ?105 ?100 ?95 ?90 gain = 20db gain = 0db gain = 40db bandwidth = 31mhz digi t al gain = 11 1 figure 36 . output noise density vs. input cw blocker level (bandwidth setting = 31 mhz, blocker at 150 mhz) ?40 ?20 0 20 40 500 1000 1500 2000 2500 0 5 10 15 20 25 30 c in (pf) r in ( ?) frequenc y (mhz) bandwidth = 31mhz 09422-038 figure 37 . input impedance vs. frequency (bandwidth setting = 31 mhz) 10 15 20 25 30 35 0 10 20 30 40 50 5 10 15 20 25 30 l series out (nh) r series out (?) frequenc y (mhz) 09422-039 bandwidth = 31mhz figure 38 . ou tput impedance vs. frequency (bandwidth setting = 31 mhz) 0 20 40 60 80 100 120 0 5 10 15 20 25 30 isol a tion (db) frequenc y (mhz) gain = 20db gain = 40db 09422-040 gain = 0db bandwidth = 31mhz figure 39 . channel isolation, outp ut to output , vs. frequency (bandwidth setting = 31 mhz) 325 330 335 340 345 350 355 360 365 0 5 10 15 20 25 30 35 i supp l y (ma) bandwidth (mhz) digi t al gain = 000 digi t al gain = 11 1 09422-041 figure 40 . current consumption at minimum and m aximum digital gain vs. bandwidth ( bandwidth setting = 31 mhz , gain = 30 db )
ADRF6516 data sheet rev. b | page 14 of 32 352 354 356 358 360 362 364 366 368 370 ?40 ?20 0 20 40 60 80 100 i supp l y (ma) temper a ture (c) digi t al gain = 000 digi t al gain = 11 1 09422-042 bandwidth = 31mhz figure 41 . current consumption at minimum and maximum digital gain vs. temperature ( bandwidth setting = 31 mhz , gain = 30 db ) 28mhz signal = 60mv p-p to 600mv p-p 200ns/div 20db gain step v gain = 750mv to 450mv bandwidth = 31mhz 09422-143 figure 42 . gain step response 0 10 20 30 40 50 60 70 0 5 10 15 20 25 30 cmrr (db) frequenc y (mhz) bandwidth = 31mhz gain = 20db gain = 40db 09422-144 figure 43 . common - mode rejection ratio (cmrr) vs. frequency (bandwidth setting = 31 mhz)
data sheet ADRF6516 rev. b | page 15 of 32 register map and cod es the filter frequency, preamplifier gain, postamplifier gain, and vga maxi mum gain can be programmed using the spi interface. table 4 provides the bit map for the internal 8 - bit register of the ADRF6516 . the p reamplifier, postamplifier, and vga maximum gai n code bits (bits[b3:b1]) are referre d to elsewhere in this data sheet as digital gain code 000 through digital gain code 111. table 4 . register map msb lsb b8 b7 b6 b5 b4 b3 b2 b1 filter frequency code p reamplifier gain cod e p ostamplifier gain code vga max gain code see table 5 0 = 3 db 1 = 6 db 0 = 6 db 1 = 12 db 0 = 22 db 1 = 28 db table 5 . frequency code vs. corner frequency lookup table 5 - bit binary frequency code 1 c orner frequency (mhz) 00000 no signal 00001 1 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 10 01011 11 01100 12 01101 13 01110 14 01111 15 5 - bit binary frequency code 1 c orner frequency (mhz) 10000 16 10001 17 10010 18 10011 19 10100 20 10101 21 10110 22 10111 23 11000 24 11001 25 11010 26 11011 27 11100 28 11101 2 9 11110 30 11111 31 1 msb first.
ADRF6516 d ata sheet rev. b | page 16 of 32 theory of operation the ADRF6516 consists of a matched pair of buffered, program - mable filters followed b y a cascade of two variable gain amplifiers and output adc drivers. the block diagram of a single channel is shown in figure 44. the programmability of the bandwidth and of the pre - and post - filtering gain through the spi interface offers great flexibility when coping with signals of varying levels in the presence of noise and large, undesired signals near by. the entire differential signal chain is dc - coupled with flexible interface s at the input and output. the ban dwidth and gain setting controls for the two channels are shared, ensuring close matching of their magnitude and phase responses. the ADRF6516 can be fully disabled through the enbl pin. 3db/6db preamp 3db/6db 11db/14db 6db/12db 1mhz to 31mhz prog. filters 25db vga 6db/12db adc driver baseband inputs baseband outputs gain and filter programming spi bus analog gain control 15mv/db 25db vga output common-mode control spi interface 09422-046 figure 44 . signal path block diagram for a single channel of the ADRF6516 filtering and amplification are fundamental operations in any signal processing system. filtering is necessary to select the int ended signal while rejecting out - of - band noise and inter - ferers. amplification increases the level of the desired signal to overcome noise added by the system. when used together, filtering and amplification can extract a low level signal of interest in t he presence of noise and out - of - band interferers. such analog signal processing alleviates the requirements on the analog, mixed signal, and digital components that follow. input buffers the input buffers provide a convenient interface to the sensitive f ilter sections that follow. they set a differential input impedance of 16 00 ? and float to a common - mode voltage near vps/2. the inputs can be dc - coupled or ac - coupled. if using direct dc coupling, the common - mode voltage presented to the inputs should be approximately vps/2 to maximize the input swing capacity. for a 3 .3 v supp ly, the common - mode voltage c an range from 1. 1 v to 1.8 v while maintaining a >65 dbc hd3 for a 400 mv p - p input signal. the vicm pin provides the optimal midsupply common - mode voltage and can be used as a refer - ence for the driving circuit. the vicm vol tage is not buffered and must be sensed at a high impedance point to prevent it from being loaded down. the input buffers in both channels can be configured simul - taneously for a gain of 3 db or 6 db through the spi (see the register map and codes section) . when configured for a 3 db gain, the buffers support a 400 m v p - p differential input level with ~ 7 0 dbc harmonic distortion. for a 6 db gain setting, the buffers support 280 mv p - p inputs. programmable filters t he integrated programmable filter is the key signal processing function in the ADRF6516 . the filters follow a six - pole butter - worth prototype response that provides a compromise between band rejection, ripple , and group delay. the 0.5 db bandwidth is programmed from 1 mhz to 31 mhz in 1 mhz steps via the serial programming interface (spi) , as described in the programming the filters and gains section. the filters are designed so that the butterworth prototype filter shape and group delay responses vs. frequency are retained for any bandwidth setting. figure 45 and figure 46 illustrate the ideal six - pole butterworth magnitude and group delay responses , respectively . the group delay, g , is defined as g = ? ?/? where : is the phase in radians . = 2f ( the frequency in radians/sec ) . note that for a frequency scaled filter prototype, the absolute magnitu de of the group delay scales inversely with the band - width; however , the shape is retained. for example, the peak group delay for a 28 mhz bandwidth setting is 14 less than for a 2 mhz setting (see figure 46) . 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 1m 10m 100m 1g relative magnitude (hz) frequency (hz) 09422-043 figure 45 . sixth - o rder butterworth magnitude response for 0.5 db b andwidths p rogrammed from 2 mhz to 29 mhz in 1 mhz steps
data sheet ADRF6516 rev. b | page 17 of 32 500 400 300 200 100 0 ?100 100k 1m 10m 100m group delay (ns) frequency (hz) bw = 2mhz bw = 28mhz 14 09422-044 figure 46. sixth-order butterworth group delay response for 0.5 db bandwidths programmed to 2 mhz and 28 mhz the corner frequency of the filters is defined by rc products, which can vary by 30% in a typical process. therefore, all the parts are factory calibrated for corner frequency, resulting in a residual 15% corner frequency variation over the ?40c to +85c temperature range. although absolute accuracy requires calibration, the matching of rc products between the pair of channels is better than 1% by observing careful design and layout practices. calibration and excellent matching ensure that the magnitude and group delay responses of both channels track together, a critical requirement for digital iq-based communication systems. variable gain amplifiers (vgas) the cascaded vgas are based on the analog devices, inc., patented x-amp? architecture, consisting of tapped 25 db attenuators followed by programmable gain amplifiers. the x-amp architecture generates a continuous linear-in-db monotonic gain response with low ripple. the analog gains of both cascaded vga sections are controlled through the high impedance gain pin with an accurate slope of 15 mv/db. the gain response shown in figure 47 shows the gain pin voltage range and the absence of gain foldback at high v gain . by changing the gains of both vgas simultaneously, a more gradual variation in noise and distortion is achieved. the fixed gain following each of the variable gain sections can also be pro- grammed to two different values to maximize dynamic range. 50 ?10 0.3 ?0.3 0 gain (db) gain error (db) v gain (v) 0 10 20 30 40 0.50 0.25 0.75 1.00 1.501.25 1.75 2.00 2.25 2.50 2.75 3.00 ?0.2 ?0.1 0 0.1 0.2 09422-049 15mv/db figure 47. linear-in-db gain control response of the x-amp vga cascade showing consistent slope and low error output buffers/adc drivers the low impedance (30 ) output buffers of the ADRF6516 are designed to drive either adc inputs or subsequent amplifier stages. they are capable of delivering up to 1.5 v p-p composite two-tone signals into 1 k differential loads with >65 dbc imd3. the output common-mode voltage defaults to vps/2, but it can be adjusted from 700 mv to 2.8 v without loss of drive capability by presenting the vocm pin with the desired common-mode voltage. the high input impedance of vocm allows the adc reference output to be connected directly. even though the output common-mode voltage is adjustable and the offset compensation loop can null the accumulated dc offsets (see the dc offset compensation loop section), it may still be desirable to ac couple the outputs by selecting the coupling cap- acitors according to the load impedance and desired bandwidth. dc offset compensation loop in many signal processing applications, no information is carried in the dc level. in fact, dc voltages and other low frequency disturbances can often dominate the intended signal and consume precious dynamic range in the analog path and bits in the data converters. these dc voltages can be present with the desired input signal or can be generated inside the signal path by inherent dc offsets or other unintended signal- dependent processes such as self-mixing or rectification. because the ADRF6516 is fully dc-coupled, it may be necessary to remove these offsets to realize the maximum signal-to-noise ratio (snr). this can be achieved with ac coupling capacitors at the input and output pins; however, large value capacitors with low impedance values are required because the high-pass corners must be <10 hz. to address the issue of dc offsets, the ADRF6516 provides an offset compensation loop that nulls the output differ- ential dc level, as shown in figure 48. if the compensation loop is not required, it can be disabled by pulling the ofds pin high.
ADRF6516 d ata sheet rev. b | page 18 of 32 gain from filters c ofs ofsx ofds 50db vga output adc driver baseband outputs 09422-050 figure 48 . offset compensation loop operates around the vga and output buffer the offset compensation loop creates a high - pass corner, f hp , that is superimposed on the normal butterworth filter response. typically, f hp is many orders o f magnitude lower than the lowest programmed filter bandwidth so that there is no interaction between them. setting f hp is accomplished with capacitors, c ofs , from the ofs 1 and ofs 2 pins to ground. because the compensation loop works around the vga section s, f hp is also dependent on the total gain of the cascaded vga s . in general, the expression for f hp is given by f hp (hz) = 6 .7 ( post filter l inear gain / c ofs ( f ) ) where post filter linear gain is expressed in linear terms, not in d ecibels (db) , and is the gain following the filters, which excludes the preamplifier gain of 1.4 (3 db) or 2 (6 db). note that f hp increase s in proportion to the gain . for this reason, c ofs should be chosen at the highest operating gain to guarantee that f hp is always below the maximum limit required by the system. programming the filt ers and gains the 0.5 db corner frequencies for both filters a nd the gains of the preamplifier s and post amplif i ers a re programmed simulta - neously through the spi port. an 8 - bit register stores the 5 - bit code for corner frequencies of 1 mhz through 31 mhz , as well as the 1 - bit codes for the preamplifier gain, the vga maximum gain, and the postamplifier gain ( see table 4 ) . the spi protocol not only allows frequency and gain codes to be written to the data pin , but it also allows the stored code t o be read back via the sdo pin. the latch enable (le) pin must first go to a l ogic 0 for a read or write cycle to begin. on the next rising edge of the clock (clk), a logic 1 on the data pin initiates a write cycle , whereas a logic 0 on the data pin initiates a read cycle. i n a write cycle, the next eight clk rising edges latch the desired 8 - bit code, lsb first. when le goes high , the write cycle is completed and the frequency and gain codes are presented to the filter and amp li - fiers . in a read cycle, the next eight clk falling edges present the stored 8 - bit code , lsb first. when le goes high, t he read cycle is completed . d etailed timing diagrams are shown in figure 2 and figure 3 . noise characteristic s the output noise behavior of the ADRF6516 d epends on the gain and bandwidth settings. figure 49 and figure 50 show the total output noise spectral density vs. frequency for different band - width settings and vga gains . ?150 ?145 ?140 ?135 ?130 ?125 ?120 ?1 15 ?1 10 5 15 25 35 45 55 65 75 85 95 output noise density (dbv/hz) frequency (mhz) bandwidth = 31mhz digi t al gain = 11 1 gain = 20db gain = 0db gain = 40db 09422-051 figure 49 . total o utput n oise density with a 31 mhz c orner f requency for three different gain settings ?150 ?145 ?140 ?135 ?130 ?125 ?120 ?1 15 ?1 10 ?105 ?100 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 output noise densit y (dbv/hz) frequency (mhz) gain = 20db gain = 0db gain = 40db bandwidth = 1mhz digi t al gain = 11 1 09422-052 figure 50 . total output noise density with a 1 mhz corner frequency for three different gain settings both the filter sections and the vgas contribute to the total noise at the output. the filter contributes a noise spectral density profile that is flat at low frequencies, peaks near the corner frequency, and then rolls off as the filter poles roll off the gain and noise. the mag nitude of the noise spectral density contributed by the filter, expressed in nv/hz, varies inversely with the square root of the bandwidth setting, resulting in a total integrated noise in nv that is nearly constant with bandwidth setting. at higher frequ encies, after the filter noise rolls off, the noise floor is set by the vgas. each of the x - amp vga sections used in the ADRF6516 con - tributes a fixed and flat noise spectral density to its respective output, independent of the gain setting. because the vgas are cascaded in the ADRF6516 , the total noise contributed by the vgas at the output increases gradually with higher gain. this is apparent in the noise floo r variation at high frequencies at different vga gain settings.
data sheet ADRF6516 rev. b | page 19 of 32 the exact relationship depends on the programmed fixed gain of the amplifiers. at minimum gain, only the last vga contributes to the ?144 dbv/hz minimum noise floor, which is equivalent to 63 nv/hz. at lower frequencies within the filter bandwidth setting, the vgas translate the filter noise directly to the output by a factor equal to the gain following the filter. at low values of vga gain, the noise at the output is the flat spectral densit y contributed by the last vga. as the gain increases, more noise from the filter and first vga appears at the output. because the intrinsic filter noise density increases at lower bandwidth settings, it is more pronounced than it is at higher bandwidth s ettings. in either case, the noise density asymptotically approaches the limit set by the vgas at the highest frequencies. for other values of vga gain and bandwidth setting, the detailed shape of the noise spectral density changes according to the relativ e contributions of the filters and vgas. because the noise spectral density outside the filter bandwidth is limited by the vga output noise, i t may be nece ssary to use an external, fixed - frequency, passive filter prior to analog - to - digital conversion to pr event noise aliasing from degrading the signal - to - noise ratio. a higher sampling rate relative to the maxi - mum required ADRF6516 corner frequency setting reduces the order and complexity of th is external filt er. distortion character istics the distortion performance of the ADRF6516 is similar to its noise performance. the filters and the vgas contribute to th e overall distortion and signal handling capabilities. f urthermore, the front end must also cope with out - of - band signals that can be larger than the in - band signals. these out - of - band signals are filtered before reaching the vga. it is important to understand the signals presented to the ADRF6516 and to match these signals with the input and output characteristics of the part. when the gain is low, the distortion is typically limited by the input section because the output is not driven to its maximum capacity. wh en the gain is high, the distortion is likely limited by the output section because the input is not driven to its maximum capacity . an exception to this is when the input is driven with a small desired signal in combination with a large out - of - band signal . in this case, the out - of - band signal may drive the input to distort. a s long as the input is not over driven, the out - of - band signal is removed by the filter. a high vga gain is still needed to raise the small desired signal to a higher level at the outpu t. the overall distortion introduced by the part depends on the input drive level, including the out - of - band signals, and the desired output signal level. as noted in the input buffers section, the input section can handle a total signal level of 400 m v p - p for a 3 db p re amp lifier gain and 28 0 mv p - p for a 6 db preamplifier gain with > 7 0 db c harmonic distortion. this includes both i n - band and out - of - band signals. t o distinguish and quantify the distortion performance of the in put section, two different ip3 specifications are presented. the first is called in - band ip3 and refers to a two - tone test where the signals are inside the filter bandwidth. this is exactly the same figure of merit familiar to communications engineers in w hich the third - order intermodulation level, imd3 , is me asured. t o quantify the effect of out - of - band signals, a new out - of - band (oob) iip3 fi gure of merit is introduced. this test also involves a two - tone stimulus; however, the two tones are placed out - of - band so that the lower imd3 product lands in th e middle of the filter pass band. at the output, only the imd3 product is visible because the original two tones are filtered out. to calculate the oob i i p3 at the input, the imd3 level is referred to the inpu t by the overall gain. the oob iip3 allows the user to predict the impact of out - of - band blockers or interferers at an arbitrary signal level on the in - band performance. the ratio of the desired input signal level to the input - referred imd3 at a given blo cker level represents a signal - to - distortion limit imposed by the out - of - band signals. maximizing the dy namic range the role of the ADRF6516 is to increase the level of a variable in - band signal while minimiz ing out - of - band signals. ideally, this is achieved without degrading the snr of the incoming signal or introducing distortion to the incoming signal . the first goal is to maximize the output signal swing , which can be defined by the adc input range or the input signal capacity of the next analog stage. for the complex waveforms often encoun - tered in communication systems, the peak - to - average ratio , or crest factor , must be considered when select ing the peak - to - peak output. from the selected output signal an d the maximum gain of the ADRF6516 , the minimum input level can be defined. lower signal levels do not yield the maximum output and suffe r a greater degradation in snr. as the input signal level increases, th e vga gain is reduced from its maximum gain point to maintain the desired fixed output level. the output noise, initially dominated by the filter, follows the gain reduction, yielding a progressively better snr. at some point, the vga gain drops sufficient ly that the vga noise becomes dominant, resulting in a slower reduction in snr from that point . from the perspective of snr alone, the maximum input level is reached when th e vga reaches its minimum gain.
ADRF6516 d ata sheet rev. b | page 20 of 32 distortion must also be considered when maximiz ing the dynamic range. at low and moderate signal levels, the output distortion is constant and assumed to be adequate for the selected output level. at some point, the input signal becomes large enough that distortion at the input limits the system. the m aximum tolerable input signal depend s on whether the input distortion becomes unacceptably large or the minimum gain is rea ched. the most challenging scenario in term s of dynamic range is the presence of a large out - of - band blocker accompanying a weaker in - band desired signal. in this case, the maximum input level is dictated by the blocker and its inclination to cause distortion. after filtering, the weak desired signal must be amplified to the desired output level, possibly requiring maximum gain. both th e distortion limits associated with the blocker at the input and the snr limits created by the weaker signal and higher gains are present simultaneously. furthermore, not only does the blocker scenario degrade the dynamic range, it also reduces the range of input signals that can be handled because a larger part of the gain range is used to simply extract the weak desired signal from the stronger blocker. key parameters for q uadrature - based receivers the majority of digital communication receivers make s use of quadrature signaling , in which bit s of information are encoded onto pairs of base band signals that then modulate in - phase (i) and quadrature (q) sinusoidal carriers. both the baseband and modulated signals appear quite complex in the time domain w ith dramatic peaks and valleys. in a typical receiver, the goal is to recover the pair of quadrature baseband signals in the presence of noise and interfering signals after quadrature demodulation . in the process of filtering out - of - band noise and un desir e d inter - ferers and restoring the level s of the desir ed i and q baseband signals, it is critical to retain their gain and phas e integrity over the bandwidth. the ADRF6516 delivers flat in - band gain and group d elay, consistent with a six - pole butterworth prototype filter , as described in the programmable filters section. furthermore, careful design ensures excellent matching of these parameters between the i and q channels. although abs olute gain flatness and group delay can be corrected with digital equalization, mismatch introduces quadrature errors and intersymbo l inter - ference that degrade bit error rates in digital communication systems.
data sheet ADRF6516 rev. b | page 21 of 32 applications informa tion basic connection s figure 51 s hows the basic connections for a typical ADRF6516 application. supply decoupling a nominal supply voltage of 3.3 v should be applied to the supply pins. the supply volta ge should not exceed 3. 4 5 v or drop below 3.15 v. each supply pin should be decoupled to ground with at least one low inductance, surface - mount ceramic capacitor of 0.1 f placed as close as p ossible to the ADRF6516 device. the ADRF6516 has two separate supplies: an analog supply and a digital supply. care should be taken to separate the analog and digital suppl ies with a large surface - mount inductor of 33 h. each supply should then be decoupled separately to its respective ground through a 10 f capacitor. input signal path each signal path has input buffers , accessed through the inp1 , inm1, inp2 , and inm2 pins , that set a differential input impedance of 1600 ?. these inputs sit at a nominal common - mode voltage around midsupply. the inputs can be dc - coupled or ac - coupled. if using direct dc coupling, the common - mode voltage, v cm , can range from 1. 1 v to 1.8 v. the vicm pin can be used as a reference common - mo de voltage for driving a high impedance sensing node of the preceding cascaded part (vicm has a 7 k? impedance) . for example, the high impedance vocm input pin of the adrf6806 quadrature demodulator can be dir ectly connected to the vicm pin of the ADRF6516 . this gives the adrf6806 the optimal common - mode voltage reference to drive the ADRF6516 . output signal path the low impedance ( 3 0 ?) output buffers are designed to drive a high impedance load, such as an adc input or another am plifier stage. the output pins opp1, opm1 , opp2 , and opm2 sit at a nominal output common - mode voltage of vps/2, but can be driven to a voltage of 0. 7 v to 2 .8 v by applying the desired common - mode voltage to the high impedance vocm pin. dc off set c ompensation loop enabled when the dc offset compensation loop is enabled via the ofds pin, t he ADRF6516 can null the output differential dc level . the loop is enabled by pulli ng the ofds pin low to ground. the offset compensation loop creates a high - pass corner frequency, which is proportional to the value of the capacitors that are connected from the ofs1 and ofs2 pins to ground. f or more information about setting the high - pass corner frequency , see the dc offset compensation loop section . common - mode bypassing the ADRF6516 common - mode pins , vicm a nd vocm, must be decoupled to ground. at least one low inductance, surface - mount ceramic capacitor with a value of 0.1 f should be used to decouple the common - mode pins. 09422-053 vpsd comd le clk data sdo com vps opp1 opm1 com gain vocm com opm2 opp2 com inp2 inm2 vps com ofds ofs2 vps enbl inp1 inm1 vps com vicm ofs1 vps ADRF6516 vps vpsd 0.1f vps vps vps vps vps output1 (+) input1 (?) 0.1f input1 (+) input2 (+) input2 (?) output1 (?) output2 (?) output2 (+) 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f serial control interface vps 0.1f figure 51 . basic connections
ADRF6516 d ata sheet rev. b | page 22 of 32 serial port connecti ons the ADRF6516 has a spi port to control the gain and filter band - width s ettings. data can be written to the internal 8 - bit register and read from the register. it is recommended that low - pass rc filtering be placed on the spi lines to filter out any high frequency glitches. see figure 58, the evaluati on board schematic, for an example of a low - pass rc filter. enable /disable function to enable the ADRF6516 , the enbl pin must be pulled hi gh. driving the enbl pin low disables the device, reducing current con sumption to approximately 9 ma at room temperature. error vector magnitu de (evm) performance error vector magnitude (evm) is a measure used to quantify the performance of a digital radio transmitter or receiver by measuring the fidelity of the digital sign al transmitted or received . v arious imperfections in the link, such as magnitude and phase imbalance , noise , and distortion, cause the constellation points to devi ate from their ideal locations. in general, a receiver exhibits three distinct evm limitation s vs. received input signal power. as signal power increases, the distortion components increase. ? at large enough signal levels, where the distortion compo - nents due to the harmonic nonlinearities in the device are falling in - band, evm degrades as signal levels increase. ? at medium signal levels, where the signal chain behaves in a linear manner and the signal is well above any notable noise contributions, evm has a tendency to reach an opti - mal level determined dominantly by either the quadrature accura cy and i q gain match of the signal chain or the p recision of the test equipment. ? as signal levels decrease, such that noise is a major con - trib ut or , evm performance vs. the signal level exhibits a decibel - for - decibel degradation with decreasing signal lev el. at these lower signal levels, where noise is the dominant limitation, decibel evm is directly proportional to the snr. evm test setup the basic setup to test evm for the ADRF6516 consisted of an agilent e 4438c used as a signal source and a hewlett - packard 89410a vector signal analyzer (vsa) used to sample and calculate the evm of the signal . the e4438c iq baseband differential outputs drove the ADRF6516 input s . the i and q outputs of the ADRF6516 were loaded with 1 k? differentia l impedances and connected differentially to two ad8130 differential amplifiers to convert the signals into single - ended signals. the single - ended signals were connected to th e input channels of the vsa . effect of filter bandwidth on evm care should be taken whe n selecting the filter bandwidth. in a digital transceiver, the modulated signal is filtered by a pulse shaping filter (such as a root - raised cosine filter) at both the transmit and receive ends to guard against intersymbol inter - ference (isi). if additional filtering of the modulated signal is done, the signal must be within the pass band of the filter. w hen the corner frequency of the ADRF6516 filter begins to encroach on the modulated signal, isi is introduced and degrades evm, which can lead to loss of signal lock . figure 52 shows that a digitally modulated qam baseband signal with a bandwidth a t 9.45 mhz has excellent evm even at a filter corner frequency of 8 mhz. further reduction in the corner frequency leads to complete loss of lock. as rf input power was swept, the ADRF6516 attained an evm of less than ?45 db over an input power range of approximately 20 db. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?25 ?20 ?15 ?10 ?5 0 5 gain vo lt age (v) evm (db) rf input power (dbm) 30mhz 15mhz 10mhz 9mhz 8mhz gain vo lt age 09422-054 figure 52 . evm vs. rf input p ower at several filter corner settings ( 256- qam , 14 msps signal with = 0.35; output differential signal level held to 700 mv p - p; ofds pulled high ) figure 53 shows the degradation that a fixed filter corner has on evm as the signal bandwidth corner is increased in fine incre ments until loss of signal lock occurs. 09422-055 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 3 4 5 6 7 8 9 10 evm (db) signa l bandwidth corner (mhz) fi l ter bandwidth corner figure 53 . evm vs. signal bandwidth corner at a filter corner of 5 mhz and a 16 - qam signal with = 0.35
data sheet ADRF6516 rev. b | page 23 of 32 effect of output voltage levels on evm output voltage level can affect evm greatly when the signal is compresse d . when changing the output voltage levels of the ADRF6516 , take care that the output si gnal is not in compres - sion, which causes evm degradation. figure 54 show evm performance vs. rf input power for several maximum differential i and q output voltage levels of 350 mv p - p up to 2.4 v p - p. for the lo wer maximum differ - ential output voltage leve ls, the evm is less than ?45 db over approximately 20 db of input pow er range. ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?25 ?20 ?15 ?10 ?5 0 5 evm (db) rf input power (dbm) 350mv p-p max 700mv p-p max 1500mv p-p max 2400mv p-p max 09422-056 figure 54 . evm vs. rf input power at several output maximum differential voltage levels ( filter corner = 10 mhz, ofds pulled high ) for the largest tes ted maximum differential output voltage level of 2.4 v p - p, the ADRF6516 begins to compress the signal. this compression causes evm to degrade, but it still remains below ?40 db, albeit over a truncated input power range. at the high end of the input power range, the signal is in full compression and evm is large. given that the gain is near its minimum, the input signal level must be lowered to bring the output signal out of full compression and into the prop er linear operating region. effect of c ofs value on evm when enabled, the dc offset compensation loop effectively nulls any information below the high - pass corner set by the c ofs capacitor. however , loss of the low frequency information of the modulated s ignal can degrade the evm in some cases. as the signal bandwidth becomes larger, the percentage of information that is corrupted by the high - pass corner becomes smaller . in such cases, it is important to select a c ofs capacitor that is large enough to mini mize the high - pass corner frequency , which prevents loss of information and degraded evm . figure 55 shows degradation of the evm vs. rf i nput power as the c ofs capacitor value becomes sm aller, which increases the h igh - pass corner for the dc offset compensation loop. ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 evm (db) rf input power (dbm) c ofs = 1f c ofs = 220nf c ofs = 1nf 09422-057 figure 55 . evm vs. rf input power at several c ofs values ( filter corner = 10 mhz , 256 - qam, 14 msps signal with = 0.35; output differential signal level held to 700 mv p - p; of ds pulled low ) figure 56 shows the effect that c ofs has on several modulated signal bandwidths. the modulated bandwidth was swept while using 1000 pf and 1 f values for c ofs . total gain was set to 15 db , so t he hi gh - pass filter corner of the 1000 pf capacitor is 26. 6 7 khz , and the high - pass filter corner of the 1 f capacitor is 26. 6 7 hz . it is recommended that at moderate signal band - widths, a 1 f capacitor for c ofs be used to obtain the best evm wh en using the d c offset compensation loop. ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 1 2 3 4 5 6 7 8 9 10 evm (db) signa l bandwidth corner (mhz) c ofs = 1f c ofs = 1000pf 09422-058 figure 56 . evm vs. signal bandwidth corner with c ofs = 1 f and c ofs = 1000 pf ( filter corner = 10 mhz )
ADRF6516 d ata sheet rev. b | page 24 of 32 evaluation board an evaluation board is available for testing the ADRF6516 . the evaluation board schematic is shown in figure 58. table 6 provides the component values and suggestions for modifying the component values for the various modes of operation. evaluation b oard c ontrol s oftware the ADRF6516 evaluation board is controlled through the parallel port on a pc. the parallel port is programmed via the ADRF6516 evaluation software. this software controls the filter corner frequency, as well as the minimum and maximum gains for each amplifier in the ADRF6516 . for information about t he register map, see table 4 and table 5 . for information about spi port timing and control, see figure 2 and figure 3 . after the evaluation software is downloaded and installed, start the basic user interface to program the filter corner and gain values (see figure 57) . to program the fi l t er corner, do one of the following: ? click the arrow in the frequency select section of the window , select the desired corner frequency from the menu , and click write bits . ? c lick freq +1 mhz o r freq ? 1 mhz to increment or decrement the corner frequency in 1 mhz steps from the current corner frequency . to program the preamplifier gain, the vga maximum gain, and the postamplifier gain, move the slider switch in the appropriate section of the window to the desired gain. ? the preamplifier gain can be set to 3 db or 6 db. ? t he vga maximum gain can be set to 22 db or 28 db. ? t he postamplifier gain can be set to 6 db or 12 db. when the user clicks the write bits button, a write operation is executed , immediate ly followed by a read operation . the updated information is displ ayed in the current pre - amp gain , current frequency , current vga max gain , and current post - amp gain fields . when the parallel port is update d with a read/write operation , the current cumulat ive maximum gain of all the ampl ifiers is displayed in the maximum gain field . (the analog vga gain is not included in this value.) because the speed of the parallel port varies from pc to pc, the clock stretch function can be used to change the effectiv e frequency of the clk line. the clk line has a scalar range from 1 to 10 ; 10 is the fastest speed, and 1 is the slowest. 09422-060 figure 57 . ADRF6516 evaluation software
data sheet ADRF6516 rev. b | page 25 of 32 schematics and a rtwork ADRF6516 vps p2 vpsd c4 0.1f vps vps vps r3 10k? p4 vps vicm c12 0.1f c14 1000pf c5 0.1f vps r12 open r1 1 open r14 open r13 open r37 open r20 0? r19 0? t3 r41 0? r39 open vposd c1 10f c2 10f l1 l2 33h 33h vpos dig_vpos vpos com comd c20 100nf r8 0? c19 100nf c16 0.1f r7 0? r5 0? r6 0? c22 r10 0? c21 100nf 100nf c18 0.1f c17 0.1f r9 0? opp1 opm1_se_ p opp2 opm2_se_ p r35 0? c24 0.1f c23 0.1f r51 open r52 open r42 0? r38 open r36 0? t4 r40 open vps c15 0.1f c13 1000pf r32 r46 open r49 0? 0? c3 0.1f r53 0? c7 100nf c8 100nf c1 1 0.1f r54 0? r50 0? r44 open t2 inp2 inm2_se_ p inm1_se_ p inp1 r31 0? r45 open r47 1 3 4 6 2 1 3 4 6 2 0? c6 0.1f r56 open r55 open r57 0? c9 100nf c10 100nf r58 0? t1 r48 0? r43 open le clk dat a sdo c29 330pf r29 100? r30 100? r33 c30 330pf r34 0? 0? r1 10k? c27 0.1f vgain vgain vocm vocm 09422-061 vpsd comd le clk d at a sdo com vps opp1 opm1 com gain vocm com opm2 opp2 com inp2 inm2 vps com ofds ofs2 vps inp1 inm1 vps com vicm ofs1 vps enb l figure 58 . evaluation board schematic
ADRF6516 data sheet rev. b | page 26 of 32 56 55 54 53 52 51 50 49 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 35 36 37 38 39 40 41 42 pd7_fd15 pd4_fd12 pd6_fd14 pd5_fd13 gnd clkout gnd vcc pa5_fifoard1 pa2_sloe reset_n pa3_wu2 pa4_fifoard0 pa6_pktend pa7_flagd_scls_n gnd vcc sda pb4_fd4 pb3_fd3 pb0_fd0 scl pb1_fd1 pb2_fd2 dplus xtalout xtalin rdy1_slwr avcc avcc agnd rdy0_slrd cy7c68013a-56 l txc u4 le 9 dminus 10 agnd 1 1 vcc 12 gnd 13 ifclk 14 reserved 23 pb5_fd5 24 pb6_fd6 27 vcc 25 pb7_fd7 26 gnd 28 gnd 29 30 31 32 33 34 ctl1_flagb pa1_int1_n ctl0_flaga ctl2_flagc vcc pa0_int0_n 48 47 46 45 44 43 wakeup vcc pd0_fd8 pd1_fd9 pd3_fd11 pd2_fd10 clk dat a 3v3_usb 3v3_usb 3v3_usb c48 10pf c49 0.1f 3v3_usb 3v3_usb r61 2k? cr2 3v3_usb r64 0? c37 0.1f c45 0.1f r62 100k? 3v3_usb y1 24mhz 3 4 2 1 c54 22pf c51 22pf 1 2 3 4 5 g1 g2 g3 g4 5v_usb p5 1 2 3 4 5 6 7 8 a0 a1 a2 gnd sda scl wc_n vcc 3v3_usb 3v3_usb 24lc64-i_sn u2 adp3334 u3 1 8 2 3 4 7 6 5 out1 out2 fb nc in2 in1 sd gnd c47 1.0f r65 2k? cr1 5v_usb r69 78.7k? c50 1000pf r70 140k? c52 1.0f 3v3_usb dgnd c35 0.1f c42 0.1f c36 0.1f c41 0.1f c40 0.1f c44 0.1f c46 0.1f 3v3_usb r60 2k? r59 2k? c38 10pf c39 0.1f sdo 09422-159 figure 59 . usb evaluation board schematic
data sheet ADRF6516 rev. b | page 27 of 32 09422-062 figure 60 . top layer silkscreen 09422-063 figure 61 . component sid e layout table 6 . evaluation board configuration options components function default conditions c1, c2, c4, c5, c11, c12, c15, c16, l1, l2 , r2 power supply and ground decoupling. nominal supply decoupling consists of a 0.1 f c apacitor to ground. c1, c2 = 10 f (size 1210) c4, c5, c11, c12, c15, c16 = 0.1 f (size 0402) l1, l2 = 33 h (size 1812) r2 = 1 k? (size 0402) t1, t2, c3, c6, c7 to c10, r31, r32, r43 to r58 input interface. input smas inp1, inm1_se_p, inp2 _se_p , and inm 2 are used to drive the part differentially by bypassing the baluns . using only inm1_se_p and in p 2_se_p in conjunction with the baluns enables single - ended operation . the default configuration of the evaluation board is for single - ended operation. t1 and t 2 are 8:1 impedance ratio baluns that transform a single - ended signal in a 50 ? system into a balanced differential signal in a 400 ? system. r31, r32, r47 , r48, r49, and r50 are populated for appropriate balun interface. r51 to r58 are provided for generic pl acement of matching components. t o bypass the t1 and t2 baluns for diff erential interfacing, remove t he balun interfacing resistors r31, r32, r47, r48, r49 , and r50, and populate r43, r44, r45, and r46 with 0 ? resistors. t1, t2 = adt8 - 1t+ (mini - circuits) c3, c6 = 0.1 f (size 0402) c7 to c10 = 100 nf (size 0 6 02) r31, r32, r4 7 to r50, r53, r54, r57, r58 = 0 ? (size 0402) r43 to r46, r51, r52, r55, r56 = open ( size 0402) t3, t4, c19 to c24, r7 to r14, r19, r20, r35 to r42 output interface. output smas opp1 _se_p, opm1, opp2, and opm2_se_p are used to obtain differential signa ls from the part when the output baluns are bypassed . using opp1 _se_p , opm2_se_p, and the baluns, the user can obtain single - ended output signals. the default configuration of the evaluation board is for single - ended operation. t3 and t4 are 8:1 impedance ratio baluns that transform a differential signal i n a 400 ? system into a single - ended signal in a 50 ? system . r7, r8, r9, r10, r19, r20, r35, r36, r41, and r42 are populated for appropriate balun interface. r7 to r14 are provided for generic placement of matching components. to bypass the t3 and t4 balu ns for differential interfacing, remove the balun interfacing resistors r19, r20, r35, r36, r41, and r42, and populate r37, r38, r39, and r40 with 0 ? resistors. t3, t4 = adt8 - 1t+ (mini - circuits) c19 to c22 = 100 nf (size 0402) c23, c24 = 0.1 f (size 0402 ) r7 to r10 , r19, r20, r35, r36, r41, r42 = 0 ? (size 0402) r11 to r14 , r37 to r40 = open (size 0402)
ADRF6516 data sheet rev. b | page 28 of 32 components function default conditions p2 enable interface. the ADRF6516 is powered up by applying a logic high voltage to the enbl pin (jumper p2 is connected to vps). p2 = installed for enable p1, c2 8 , c2 9 , r1, r29, r30, r33, r34 serial c ontrol interface. the digital interface set s the corner frequency, the pre amp lifier gain, the postamplifier gain , and the vga max imum gain of the device using the serial interface via the le, clk, data, and sdo pins . rc filter networks are provided on the clk and le lines to filter the pc signals. clk, data, and le signals can be observed via smb connectors for debug purposes . p1 = installed r1 = 10 k? (size 0402) c2 8 , c29 = 330 pf (size 0402) r29, r30 = 100 ? (size 0402) r33, r34 = 0 ? (size 0402) p4, c13, c14, r3 dc offset co mpensa tion loop. the dc offset compensation loop is enabled (low) with jumper p4. when enabled, the c13 and c14 capacitors ar e connected to circuit common. the high - pass corner frequency is expressed as follows: f hp (hz) = 6.7 ( post filter l inear gain / c ofs (f)) p4 = installed c13, c14 = 1000 pf (size 0402) r3 = 10 k? (size 0402) c27 input common - mode setpoint. the input com mon - mode voltage can be set externally when applied to the vicm pin. if the vicm pin is left open, the input common - mode voltage defaults to vps/2. c27 = 0.1 f (size 0402) c18, r 6 output common - mode setpoint. the output common - mode voltage can be set ext ernally when applied to the vocm pin. if the vocm pin is left open, the output common - mode voltage defaults to vps/2. c18 = 0.1 f (size 0402) r6 = 0 ? (size 0402) c17, r5 analog gain control. the range of the gain pin is from 0 v to 1 v, creating a gain scaling of 15 mv/db. c17 = 0.1 f (size 0402) r5 = 0 ? (size 0402) u2, u3, u4 , p5 cypress microcontroller, eeprom , and ldo u2 = microchip micro24lc64 u3 = a nalog d evices adp3334acpz u4 = cypress semiconductor cy7c68013a - 56 lt xc p5 = mini usb c onnector c35, c36, c40, c41, c42, c44, c46 3.3 v s upply decoupling. several capacitors are used for decoupling on the 3.3 v supply. c35, c36, c40, c41, c42, c44, c46 = 0.1 f (0402) c48, c49, c45, c56, c57, c58, r 5 9, r60, r61, r62, r64, cr2 cypress and eeprom c omponents. c 57 , c48 = 10 pf (0402) c56 , c 58 , c45, c49 = 0.1 f (0402) r59, r60, r61 = 2 k? (0402) r62, r64 = 100 k? (0402) cr2 = rohm sml - 21omtt86 c47, c5 0, c52, r65, r69, r70, cr1 ldo c omponents c47, c52 = 1 f (0402) c50 = 1000 pf (0402) r65 = 2 k? (0402) r69 = 78.7 k? (0402) r70 = 140 k? (0402) cr1 = rohm sml - 21omtt86 y1, c51, c54 crystal o s cillator and components. 24 mhz crystal oscillator. y1 = ndk n x3225sa - 24mhz c51, c54 = 22 pf (0402)
data sheet ADRF6516 rev. b | page 29 of 32 outline dimensions 3.25 3.10 sq 2.95 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards mo-220-vhhd-2 1 32 8 9 25 24 17 16 coplanarity 0.08 3.50 ref 0.50 bsc pin 1 indicator pin 1 indicator 0.30 0.25 0.18 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom s eating plane 0.50 0.40 0.30 5.00 bsc sq 4.75 bsc sq 0.60 max 0.60 max 0.25 min 05-25-2011-a top view exposed pad bottom view figure 62. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADRF6516acpz-r7 ?40c to +85c 32-lead lfcsp_vq, 7 tape and reel cp-32-2 ADRF6516-evalz evaluation board 1 z = rohs compliant part.
ADRF6516 data sheet rev. b | page 30 of 32 notes
data sheet ADRF6516 rev. b | page 31 of 32 notes
ADRF6516 data sheet rev. b | page 32 of 32 notes ? 2010 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09422 - 0- 2/12(b)

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